1. Field of Invention
The present invention relates to a flash memory cell and fabricating method thereof, and more particularly, to a flash memory cell for tunneling electrons stored in a floating gate with an erasing gate, and a method of fabricating of the same.
2. Discussion of the Related Art
A flash memory cell is an inactive memory device having a floating gate and a control gate, the control gate being positioned over the floating gate. The memory cells of an array of flash memory cells are erased simultaneously and the speed of erasing is outstandingly fast.
To program a flash memory cell, hot-electrons are injected into the channel by applying high voltage to the control gate and into the floating gate. A coupling ratio is defined by the voltage applied to the floating gate over the other voltage applied to the control gate. The more the coupling ratio increases, the more efficient the program becomes.
The flash memory cell is erased by injecting the electrons of the floating gate into the source region of the semiconductor substrate to which high voltage is applied according to the tunneling mechanism of Fowler-Nordheim. Moreover, the erasing operation can be achieved by tunneling the electrons stored in floating gate into the erasing gate with extra floating gate.
The thickness of the portion of the gate insulating film lying under the floating gate is decreased to improve the efficiency of the erasing operation. The decreased thickness of the film effectively lowers the voltage applied to the floating gate due to the decreased coupling ratio. Hence, the efficiency of the erasing operation for the programming is increased while the coupling ratio is maintained.
FIG. 1 shows a cross-sectional view of a conventional flash memory cell. To fabricate the flash memory cell of FIG. 1, a floating gate 15 is formed having a gate insulating layer 13 underneath. To form the floating gate 15, a polycrystalline layer doped with impurities is patterned. After forming floating gate 15, a control gate 19 is formed on floating gate 15, a second gate insulating layer 17 being formed therebetween, wherein the control gate 19 is defined to have a striped pattern that is crossed by the direction of channel length. Thereafter, a sidewall spacer 25 is formed at the lateral surface of the first gate insulating layer 13, the floating gate 15, the second gate insulating layer 17 and the control gate 19.
A source region 27 and a drain region 29, which are doped heavily with N typed impurities, are then formed in the substrate 11 under both sides of the floating gate 15. A lightly doped region 23 with an N-type impurity is formed right below the source region 27 in the semiconductor substrate 11. The flash memory cell having the above-mentioned structure operates is programmed as follows.
First, a gate voltage Vg of 12 V is applied to the control gate 19, a drain voltage Vd of 5 to 6 V is applied to the drain region 29 while the source region 27 is grounded. Thus, a channel is formed under the floating gate 15 in the semiconductor substrate 11 by the gate voltage Vg which has been applied to the control gate 19, and electrons accelerated by the drain voltage Vd applied to the drain region 29 are injected into the floating gate 15 over the energy barrier of the first gate insulating layer 13. Since the threshold voltage of the cell has increased based on the injection of electrons into the floating gate 15, programming is completed.
However, when operated in this manner, the efficiency of the programming depends on the value of the voltage induced from the gate voltage Vg which has been applied to the control gate 19. Namely, the larger the coupling ratio determined by the voltage induced to the floating gate 15 over the gate voltage Vg applied to the control gate 19, the more efficient the programming becomes. The coupling ratio increases provided the capacitance of the first gate insulating layer 13 is relatively small or the capacitance of the second gate insulating layer 17 is relatively large. Hence the second insulating layer 17 is formed with a structure of O--N--O (oxide-nitride-oxide) layer to increase its capacitance.
In order to erase data programmed in the flash memory cell, the electrons in the floating gate 15 are tunneled into the heavily-doped source region 27 by applying a source voltage Vs of greater than 15 V to the lightly-doped source region 23 while the control gate 19 is grounded or provided with negative voltage. The electrons migrate from the floating gate 15 to the source region 27 through the first gate insulating layer 13 based on Fowler-Nordheim tunneling, thereby lowering the threshold voltage of the cell and erasing the cell. In addition, the lightly-doped source region 23 prevents the application of high voltages to the heavily doped source region 27 during junction breakdown since it diffuses the junction deeply. The first gate insulating layer 13 is formed thin to improve the efficiency for erasing the cell since the electrons migrate from the floating gate 15 to the heavily doped source region 27 through the first gate insulating layer 13.
FIGS. 2A to 2D show a cross-sectional view of steps in the process of fabricating the above-described flash memory cell according to the prior art.
Referring to FIG. 2A, a first gate insulating layer 13 is formed by thermal oxidation of the surface of a P-type semiconductor substrate 11. A polycrystalline silicon layer doped with impurity is deposited on the first gate insulating layer 13 with CVD (Chemical Vapor Deposition). A floating gate 15, which has striped pattern in a first direction determined by the channel length, is formed by patterning the polycrystalline silicon layer via photolithography.
Referring to FIG. 2B, a second gate insulating layer 17 comprising oxide-nitride-oxide is formed to cover the floating gate 15. A control gate 19 is then formed on the second gate insulating layer 17 by depositing polycrystalline silicon doped with impurity by CVD.
Referring to FIG. 2C, the control gate 19, the second gate insulating layer 17, the floating gate 15 and the first gate insulating layer 13 are sequentially patterned, via photolithography, in a second direction defined perpendicular to the first direction. A photoresist pattern 21 exposing a certain part of the semiconductor substrate 11 is then defined, and a lightly-doped region 23 is formed by implanting an N-type impurity into the exposed part of the semiconductor substrate 11. The exposed part of the substrate 11, into which regions 23 is formed, is not protected by the photoresist pattern 21 which acts as a mask. The edge of the lightly-doped region 23 overlaps part of the floating gate 15 due to diffusion and the like.
Referring to FIG. 2D, the photoresist pattern 21 is removed, and an oxide is deposited on the semiconductor substrate 11 with CVD to cover the control gate 19. Then, a sidewall spacer 25 is formed at the lateral surfaces of the first gate insulating layer 13, the floating gate 15, the second insulating layer 17 and the control gate 19. Using the control gate 19 and the sidewall spacer 25 as a mask, a source region 27 and a drain region 29 are formed by implanting large amounts of an N-type impurity into the semiconductor substrate 11, wherein the source region 27 is positioned over the lightly-doped region 23.
However, through this process, the efficiency of the programming decreases due to the decline of the coupling ratio since the capacity of the first gate insulating layer is enhanced by its thin construction, a construction that is used by the conventional system to improve the erasing efficiency.
Additionally, the reliability of the conventional flash memory cell is poor since the data programmed in the floating gate may be erased by the drain voltage, and the construction is complicated since it is difficult to form the first insulating layer thin. Moreover, the dimension of device swells and the process becomes further complicated in erasing operation since the lightly-doped region 23 is necessary for preventing the destruction of the source junction from the high voltage applied to the source region.